Electrically Erasable and Programmable Read-Only Memory (EEPROM) devices are Non-Volatile Memory (NVM) devices that are erased and programmed using electrical signals. An EEPROM device typically includes several thousand memory cells organized in an array. In general, a memory cell includes a floating gate transistor and a select transistor. This configuration is referred to as a two-transistor EEPROM cell. The select transistor in an EEPROM device is used to select memory cells that are to be erased or programmed. A selected memory cell refers to a memory cell that is either being programmed, erased, or read. On the other hand, unselected memory cells are the memory cells of the array that are not selected for programming, erasing, or reading. The floating gate transistors in the device are those transistors that store the digital data in each memory cell. Typically, the digital data is stored as eight bit words called bytes. Each byte may be individually programmed and erased.
To program and erase memory cells, a phenomenon known as Fowler-Nordheim (FN) tunneling is commonly used to store either a positive or a negative charge on the floating gate electrode of the floating gate transistor. For example, programming is accomplished by applying a positive voltage to the drain and the gate of the select transistor while a control gate of the floating gate transistor is held at ground potential. As a result, electrons tunnel from the floating gate of the floating gate transistor through a tunnel dielectric to the drain, leaving the floating gate positively charged.
A disadvantage with two-transistor EEPROM cells is that the gate oxide thickness of the floating gate transistor is different from the gate oxide thickness of the select transistor. The floating gate transistor has a thinner gate oxide to allow electron tunneling through the gate oxide, whereas the select transistor has a thicker gate oxide to sustain large programming voltages. The thicker gate oxide of the select transistors causes the access time of the memory cell to be relatively long.
Prior art memory arrays are configured such that their memory cells are arranged in rows and columns. Typically, the gates of the transistors within the same row are connected to each other and to a common word line. Similarly, the drain electrodes of the transistors within the same column are connected to each other and to a common bit line. In addition, the source electrodes of the transistors are typically connected to each other via a common source line.
To program a selected memory cell in a selected row and a selected column, a programming voltage is applied to either or both the word line or the bit line which is connected to the selected memory cell. Well known problems referred to as "gate-disturb," "drain-disturb," and "source-disturb" events can occur when programming the selected cell. A gate-disturb event occurs in unselected memory cells that are connected to the same word line as the selected memory cell. During programming, the unselected memory cells in the same row as the selected memory cell also have the programming voltage applied to their gates. Thus, electrons may tunnel through the tunnel dielectrics of the unselected memory cells, unintentionally programming them. A drain-disturb event occurs in unselected memory cells that are connected to the same bit line as the selected memory cell. During programming, the unselected memory cells in the same column as the selected memory cell may have a high electric field applied between their floating gates and drains. This causes electrons to unintentionally tunnel between the floating gate and the drain of the unselected memory cell. Similarly, since the source electrodes of the selected and unselected cells are connected to each other, a source-disturb event can occur in unselected memory cells.
Accordingly, it would be advantageous to have a non-volatile memory device that prevents disturb problems in unselected memory cells. It would be of further advantage to have a method for manufacturing the non-volatile memory device that is compatible with standard semiconductor processing techniques and is cost efficient.